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THC63LVDM83D _rev.3.1_e copyright?2011 thine electronics, inc. 1/12 thine electronics, inc. block diagram 7 THC63LVDM83D reduced swing lvds 24bit colo r host-lcd panel interface general description the THC63LVDM83D transmitter is designed to sup- port pixel data transmission between host and flat panel display from ntsc up to 1080p(60hz). the THC63LVDM83D converts 28bits of cmos/ttl data into lvds(low voltag e differential signaling) data stream. the transmitter can be programmed for ris- ing edge or falling edge clocks through a dedicated pin. at a transmit clock frequency of 160mhz, 24bits of rgb data and 4bits of timing and control data (hsync, vsync, cntl1, cn tl2) are transmitted at an effective rate of 1120mbps per lvds channel. features ? wide dot clock range: 8-160mhz suited for ntsc, vga, svga, xga,sxga and sxga+ ? pll requires no external components ? supports spread spectrum clock generator ? on chip jitter filtering ? clock edge selectable ? supports reduced swing lvds for low emi ? power down mode ? low power single 3.3v cmos design ? low profile 56 lead tssop package ? 1.2 up to 3.3v tolerant data inputs to connect directly to low power,low voltage application and graphic processor. ? pin compatible with thc63lvdm83c/83r(24bits) ttl parallel to serial pll ta +/- tb +/- tc +/- td +/- tclk +/- r/f /pdwn ta0-6 tc0-6 td0-6 transmitter (8 to 160mhz) cmos/ttl 7 rs 7 tb0-6 7 inputs clock (lvds) 8-160mhz data (lvds) (56-1120mbit/on each lvds channel) clkin THC63LVDM83D
copyright?2011 thine electronics, inc. 2/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 rs td1 ta5 ta6 gnd tb0 tb1 td2 vcc td3 tb2 tb3 gnd tb4 tb5 td4 r/f td5 tb6 tc0 gnd tc1 tc2 tc3 td6 vcc tc4 tc5 ta4 ta3 ta2 gnd ta1 ta0 td0 lvds gnd ta- ta+ tb- tb+ lvds vcc lvds gnd tc- tc+ tclk- tclk+ td- td+ lvds gnd pll gnd pll vcc pll gnd /pdwn clk in tc6 gnd THC63LVDM83D
copyright?2011 thine electronics, inc. 3/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e pin description pin name pin # type description ta+, ta- 47, 48 lvds out lvds data out. tb+, tb- 45, 46 lvds out tc+, tc- 41, 42 lvds out td+, td- 37, 38 lvds out tclk+, tclk- 39, 40 lvds out lvds clock out. ta0 ~ ta6 51, 52, 54, 55, 56, 3, 4 in pixel data inputs. tb0 ~ tb6 6, 7, 11, 12, 14, 15, 19 in tc0 ~ tc6 20, 22, 23, 24, 27, 28, 30 in td0 ~ td6 50, 2, 8, 10, 16, 18, 25 in /pdwn 32 in h: normal operation, l: power down (all outputs are hi-z) rs 1 in lvds swing mode, vref select.see fig4, 5. r/f 17 in input clock triggering edge select. h: rising edge, l: falling edge vcc 9, 26 power power supply pins for ttl inputs and digital circuitry. clkin 31 in clock in. gnd 5, 13, 21, 29, 53 ground ground pins for ttl inputs and digital circuitry. lvds vcc 44 power power supply pins for lvds outputs. lvds gnd 36, 43, 49 ground ground pins for lvds outputs. pll vcc 34 power power supply pin for pll circuitry. pll gnd 33, 35 ground ground pins for pll circuitry. rs lvds swing small swing input support vcc 350mv n/a 0.6 ~ 1.4v 350mv rs=vref a gnd 200mv n/a a. vref is input reference voltage.
THC63LVDM83D _rev.3.1_e copyright?2011 thine electronics, inc. 4/12 thine electronics, inc. absolute maximum ratings 1 supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) cmos/ttl output voltage -0.3v ~ (v cc + 0.3v) lvds transmitter output voltage -0.3v ~ (v cc + 0.3v) output current continuous junction temperature +125 storage temperature range -55 ~ +150 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 1.8w 1. ?absolute maximum ratings? are those valued beyond whic h the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of ?electrical characteristics? specify conditions for device operation. c c c c c
copyright?2011 thine electronics, inc. 5/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e electrical characteristics cmos/ttl dc specifications v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 notes: 1 v ddq voltage defines max voltage of small swing input. it is not an actual input voltage. 2 small swing signal is applied to ta0-6,tb0-6,tc0-6,td0-6 and clkin. lvds transmitter dc specifications v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 symbol parameter conditions min. typ. max. units v ih high level input voltage rs=vcc or gnd 2.0 v cc v v il low level input voltage rs=vcc or gnd gnd 0.8 v v ddq 1 small swing voltage 1.2 2.8 v v ref input reference voltage small swing (rs=v ddq /2) v ddq /2 v sh 2 small swing high level input voltage v ref = v ddq /2 v ddq /2 +100mv v v sl 2 small swing low level input voltage v ref = v ddq /2 v ddq /2 -100mv v i inc input current a symbol parameter conditions min. typ. max. units vod differential ou tput voltage rl=100 normal swing rs=v cc 250 350 450 mv reduced swing rs=gnd 100 200 300 mv vod change in vod between complementary output states rl=100 35 mv voc common mode voltage 1.125 1.25 1.375 v voc change in voc between complementary output states 35 mv i os output short circuit current vout=0v, rl=100 -24 ma i oz output tri-state current /pdwn=0v, v out =0v to v cc a c c 0v v in v cc ? 10 c c 10
copyright?2011 thine electronics, inc. 6/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e supply current v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 symbol parameter condition(*) typ. max. units i tccw transmitter supply current rl=100 ,cl=5pf v cc =3.3v, rs=v cc worst case pattern f=85mhz 61 67 ma f=135mhz 77 83 ma f=160mhz 84 92 ma rl=100 ,cl=5pf v cc =3.3v, rs=gnd worst case pattern f=85mhz 50 56 ma f=135mhz 65 71 ma f=160mhz 73 80 ma i tccs transmitter power down supply current /pdwn = l, all inputs = l or h 10 a c c clkin tx0 worst case pattern tx1 tx2 tx3 tx4 tx5 tx6 x= a, b, c, d fig1. worst case pattern
copyright?2011 thine electronics, inc. 7/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e switching characteristics v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 symbol parameter min. typ. max. units t tcit clk in transition time 5.0 ns t tcp clk in period 6.25 t 125 ns t tch clk in high time 0.35t 0.5t 0.65t ns t tcl clk in low time 0.35t 0.5t 0.65t ns t tcd clk in to tclk+/- delay 3t ns t ts ttl data setup to clk in 2.0 ns t th ttl data hold from clk in 0.0 ns t lvt lvds transition time 0.6 1.5 ns t top1 output data position0 (t=6.25ns~20ns) -0.15 0.0 +0.15 ns t top0 output data position1 (t=6.25ns~20ns) ns t top6 output data position2 (t=6.25ns~20ns) ns t top5 output data position3(t=6.25ns~20ns) ns t top4 output data position4 (t=6.25ns~20ns) ns t top3 output data position5 (t=6.25ns~20ns) ns t top2 output data position6 (t=6.25ns~20ns) ns t tpll phase lock loop set 10.0 ms c c t 7 --- 0 . 1 5 ? t 7 --- t 7 --- 0 . 1 5 + 2 t 7 --- 0 . 1 5 ? 2 t 7 --- 2 t 7 --- 0 . 1 5 + 3 t 7 --- 0 . 1 5 ? 3 t 7 --- 3 t 7 --- 0 . 1 5 + 4 t 7 --- 0 . 1 5 ? 4 t 7 --- 4 t 7 --- 0 . 1 5 + 5 t 7 --- 0 . 1 5 ? 5 t 7 --- 5 t 7 --- 0 . 1 5 + 6 t 7 --- 0 . 1 5 ? 6 t 7 --- 6 t 7 --- 0 . 1 5 + ac timing diagrams ttl input 5pf 20% 80% 20% 80% t lvt t lvt clk in lvds output 90% 10% 90% 10% t tcit t tcit v diff 100 v diff =(ta+)-(ta-) ta+ ta- lvds output load fig2. clkin transition time fig3. lvds output load and transition time
copyright?2011 thine electronics, inc. 8/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e ac timing diagrams ttl inputs t tcp t ts t th t tch t tcl clk in tx0-tx6 t tcd note: clk in: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. tclk+ tclk- small swing inputs t tcp t ts t th t tch t tcl clk in tx0-tx6 t tcd note: clk in: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. tclk+ tclk- v ddq gnd gnd v ddq v ref voc voc v ref vcc/2 vcc/2 vcc/2 vcc/2 v ddq /2 v ddq /2 v ddq /2 v ddq /2 v ddq /2 vcc/2 fig4. clkin period, high/low time, setup/hold timing fig5. small swing inputs vcc gnd gnd vcc rs pin vod vcc 350mv 0.6~1.4v gnd 200mv vod rs pin vref vcc vcc/2 0.6~1.4v input voltage of rs pin gnd vcc/2
copyright?2011 thine electronics, inc. 9/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e ac timing diagrams phase lock loop set time v diff = 0v v diff = 0v tclk+/- t top1 t top0 t top6 t top5 t top4 t top3 t top2 lvds output td6 td5 td4 td3 td2 td1 td0 td+/- tc6 tc5 tc4 tc3 tc2 tc1 tc0 tc+/- tb6 tb5 tb4 tb3 tb2 tb1 tb0 tb+/- ta6 ta5 ta4 ta3 ta2 ta1 ta0 ta+/- (differential) next cycle previous cycle fig6. lvds output data position 2.0v clkin /pdwn tclk+/- 3.0v 3.6v vcc t tpll v diff = 0v fig7. pll lock set time
copyright?2011 thine electronics, inc. 10/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e note 1)cable connection and disconnection don't connect and disconnect the lvds cable, when the power is supplied to the system. 2)gnd connection connect the each gnd of the pcb which THC63LVDM83D and lvds-rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3)multi drop connection multi drop connection is not recommended. 4)asynchronous use asynchronous use such as foll owing systems are not recommended. lvds-rx THC63LVDM83D lvds-rx tclk+ tclk- THC63LVDM83D THC63LVDM83D ic clkout clkout data data lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVDM83D THC63LVDM83D ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic
copyright?2011 thine electronics, inc. 11/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e package 0.50 typ 0.17~0.27 14.00 0.10 1 0.25 gage plane 0.60 0.15 1.00 0.10 0.05 0.95 0.05 1.20 max detail of lead end unit:mm 0~8 s 0.10 s 8.10 0.10 6.10 0.10
copyright?2011 thine electronics, inc. 12/12 thine electronics, inc. THC63LVDM83D_rev.3.1_e notices and requests 1. the product specifications descri bed in this material are subjec t to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possi ble errors and omissions in this material. please note if errors or omissions should be fo und in this material, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other propr ietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third part y's industrial ownership s hould occur by using this product, we will be exempted fro m the responsibility unless it di rectly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equi pment, not for the applications which require very high reliability (including medical equipment direct ly concerning people's life, aerospace equipment, or nuclear control eq uipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after ap plying appropriate measures to the product. 6. despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small pr obability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign ex change and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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